Sony 3ClearVid CMOS Technology Primer

In this installment of HDV@Work, we look at the technology behind Sony's ClearVid CMOS chips, found in the new HVR-V1U camcorder. In the last installment, we looked at five aspects of CMOS technology. First, we looked at how CMOS chips function. Second, we saw how exposure control is implemented — including how the ability to simultaneously read multiple elements from a CMOS chip reduces the possibility of the “rolling shutter” artifact. Third, Correlated Double Sampling (CDS) was shown to be a common method of reducing Fixed Pattern Noise (FPN) that results from each CMOS element having its own on-chip amplifier. Fourth, we explored how extra circuits on a chip can increase latitude. (ClearVid does not use this technology.) Last, we learned that the chip element-count determines the cut-off frequency for the anti-alias low-pass filter that is what really limits image resolution.

In the illustration below, we can see that only a portion of a CMOS element actually captures light. The area of the photodiode divided by the element''s total area is called its “fill factor.” (It''s possible that when Sony claims V1''s ClearVid elements have the “same area” as the Z1''s CCD elements, they are talking about fill factor percentages.)

Most CMOS imagers today use Active Pixel Sensor technology (APS), which requires at least three transistors to implement. (These are called 3T devices.) There is no reason to believe ClearVid is any different. Sony illustrates its ClearVid technology using the diagram below.

Each CMOS element is rotated 45 degrees. Despite the rotation, the elements are “square.” Because the ClearVid chips used in the V1/FX7 have a resolution of about 1000x1000 and have a 16:9 aspect ratio, we know the idealized elements above cannot be an accurate representation.

ClearVid elements most likely look like the squat diamond shown below. The photodiode area is shown outlined in yellow. (This example has about a 33-percent fill factor. Sony claims a very high fill factor.)

In my crude diagram below, you can see how such an element can support an equal number of elements on each axis and fill a 16:9 space.

Despite the rotation of elements, elements are read out row-by-row as shown below. Elements are read out into Sony''s Enhanced Image Processing chip (EIP).

According to Sony Japan, four elements — from four columns — are read simultaneously from each ClearVid chip into each of the EIP''s three 2-million cell buffers. By outputting four elements at a time, read-out speed is increased by a factor of four, thereby eliminating, or at least significantly reducing, the rolling-shutter artifact. (Read-out speed is “X” in the last installment''s section on exposure control.)

When a row is output, each element sends its signal down its column bus where it is input to a Sample & Hold circuit that briefly stores the value. (There is a Sample & Hold for each column.) Next, a second cycle is performed on the same row. Immediately, all row elements are sent down to a second set of Sample & Hold circuits. The second set of values is measures of each element''s inherent noise. The first set of values is measures of element signal+noise values. Now all stored noise values are subtracted from all signal+noise values to yield a row of signal values. This system is called Correlated Double Sampling (CDS). Sony uses this type of CDS. The output from a ClearVid chip is an analog signal that is converted to a digital signal by a 14-bit A-to-D converter in the Digital eXtended Processor (DXP). The DXP chip uses 14-bit words for baseband signal processing — for example, for noise reduction.

The diagram below shows eight elements that lie in two rows. The elements in odd rows — labeled A, B, C, and D — are read out simultaneously. This occurs 135 times for the 540 elements in each row. All elements in Row 1 are read out before all elements in Row 2 are read out.

The elements in even rows — labeled W, X, Y, and Z — are also read out simultaneously. Again, this occurs 135 times for the 540 elements in each even row.

			1	2	3	4	5	6	7	8
ROW 1	LINE 1		1A		1B		1C		1D
ROW 2	LINE 1	LINE 2		2W		2X		2Y		2Z
ROW 3	LINE 3	LINE 2	3A		3B		3C		3D
ROW 4	LINE 3	LINE 4		4W		4X		4Y		4Z
ROW 5	LINE 5	LINE 4	5A		5B		5C		5D
ROW 6	LINE 5	LINE 6		6W		6X		6Y		7Z
ROW 7	LINE 7	LINE 6	7A		7B		7C		7D
ROW 8	LINE 7	LINE 8		8W		8X		8Y		8Z
ROW 9		LINE 8	9A		9B		9C		9D

The first two rows to be read out are Rows 1 and 2. The next rows to be read out are Rows 3 and 4. The read-out process works down the chip as shown below.